p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 1 6 0 v p - c hannel enhancement mode mosfet v oltage - 6 0 v c urrent - 16 a dfn5060 - 8l f eatures ? r ds(on) , v gs @ - 10v,i d @ - 8 a< 48m ? r ds(on) , v gs @ - 4.5 v,i d @ - 4 a< 65m ? high switching speed ? improved dv/dt capability ? low gate charge ? low reverse transfe r capacitance ? lead free in compliance with eu rohs 2011/65/eu directive. ? green molding compound as per iec61249 std. (halogen free) m echanical data ? case: dfn5060 - 8l package ? terminals: solderable per mil - std - 750, method 2026 ? approx. weight: 0.00 28 ounces, 0.0 8 grams ? marking: q54 65 a m a ximum r atings and t hermal c haracteristics (t a =25 o c unless otherwise noted) parameter symbol limit units drain - source voltage v ds - 60 v gate - source voltage v gs + 2 0 v continuous drain current t c =25 o c i d - 1 6 a t c = 100 o c - 10 pulsed drain current (note 1 ) t c =25 o c i dm - 64 power dissipation t c =25 o c p d 2 5 w t c = 100 o c 10 continuous drain current t a =25 o c i d - 5.0 a t a = 70 o c - 4.0 a power dissipation t a =25 o c p d 2.0 w power dissipation t a = 70 o c 1.3 single pulse avalanche energy (note 6 ) e as 51 mj operating junction and storage temperature range t j ,t stg - 55~1 50 o c typical thermal r esistance (note 4,5 ) junction to case r jc o c /w j unction to ambient r ja 6 2 .5 ? limited only by maximum junction temperature
p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv d ss v gs =0v,i d = - 250ua - 6 0 - - v gate threshold voltage v gs(th) v ds =v gs ,i d = - 250ua - 1. 0 - 1. 7 - 2.5 v drain - source on - state resistance r ds(on) v gs = - 10v,i d = - 8 a - 40 48 m gs = - 4.5 v,i d = - 4 a - 55 65 zero gate voltage drain current i dss v ds = - 60 v,v gs =0v - - - 1 . 0 ua gate - source leakage current i gss v gs = + 2 0v,v ds =0v - - + 100 n a dynamic (note 7 ) total gate charge q g v ds = - 30 v, i d = - 8 a, v gs = - 10 v (note 3 ) - 22 - nc gate - source charge q gs - 4.1 - gate - drain charge q gd - 5.2 - input capacitance ciss v ds = - 30 v, v g s =0v, f=1.0mhz - 125 6 - pf output capacitance coss - 8 7 - reverse transfer capacitance crss - 59 - turn - on delay time td (on) v dd = - 30 v, i d = - 1 a, v g s = - 10v, r g = 6 (note 3 ) - 13 - ns turn - on rise time t r - 42 - turn - off delay time td (off) - 65 - turn - off fall time t f - 1 6 - drain - source diode maximum continuous drain - source diode forward current i s --- - - - 1 6 a diode forward voltage v sd i s = 1 a,v gs =0v - - 0. 7 2 - 1. 0 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. repetitive rating, pulse width limited by junction temperature tj(max)=150c. ratings are based on low frequency and duty cyc les to keep initial t j =25c. 4. the maximum current rating is package limited. 5. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. m ount ed on a 1 inch 2 with 2oz. square pad of copper . 6. the test condition is l=0.1mh, i as = 32 a , v dd = 25v, v gs =10v 7. guaranteed by design, not subject to product ion testing.
p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 3 t ypical characteristic curves fig.1 output characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 on - resist a nce vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 source - drain diode forward voltage
p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 4 t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 breakdown voltage variation vs. temperature fi g. 9 threshold voltage variation with temperature fig. 10 capacitance vs. drain - source voltage fig. 11 maximum safe operating area
p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 5 t ypical characteristic curves fig. 12 normalized transient thermal impedance vs. pulse width
p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 6 part no packing code version packaging information & mounting pad layout dfn5060 - 8l dimensi on u nit: mm dfn5060 - 8l pad la y out u nit: mm part n o packing code package type packing type marking ver sion pjq5465 a_r 2 _00001 dfn5060 - 8l 3000 pcs / 13
p p j q546 5 a jul y 2 1 ,201 5 - rev.0 0 page 7 disclaimer
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